1. Field of the Invention
The present invention relates to an overcurrent protection circuit of a voltage regulator.
2. Description of the Related Art
A related-art voltage regulator is now described. FIG. 3 is a circuit diagram illustrating the related-art voltage regulator.
The related-art voltage regulator includes a reference voltage circuit 111, a differential amplifier circuit 112, an overcurrent protection circuit 130, a PMOS transistor 113, a resistor 114, a resistor 115, a ground terminal 101, a power supply terminal 102, and an output terminal 103. The overcurrent protection circuit 130 includes a PMOS transistor 131, an NMOS transistor 132, a differential amplifier circuit 133, a resistor 134, and a control circuit 140. The control circuit 140 includes a PMOS transistor 141, a differential amplifier circuit 142, and a resistor 143.
The differential amplifier circuit 112 has an inverting input terminal connected to the reference voltage circuit 111, a non-inverting input terminal connected to a node between the resistor 114 and the resistor 115, and an output terminal connected to a gate of the PMOS transistor 113. The PMOS transistor 113 has a source connected to the power supply terminal 102, and a drain connected to the output terminal 103. The resistor 114 and the resistor 115 are connected between the output terminal 103 and the ground terminal 101. The PMOS transistor 131 has a gate connected to the output terminal of the differential amplifier circuit 112, a source connected to the power supply terminal 102, and a drain connected to a drain of the NMOS transistor 132. The differential amplifier circuit 133 has a non-inverting input terminal connected to the non-inverting input terminal of the differential amplifier circuit 112, an inverting input terminal connected to a source of the NMOS transistor 132, and an output terminal connected to a gate of the NMOS transistor 132. The resistor 134 is connected between the source of the NMOS transistor 132 and the ground terminal 101. The differential amplifier circuit 142 has a non-inverting input terminal connected to the reference voltage circuit 111, an inverting input terminal connected to the drain of the NMOS transistor 132, and an output terminal connected to a gate of the PMOS transistor 141. The resistor 143 is connected between the inverting input terminal of the differential amplifier circuit 142 and the ground terminal 101. The PMOS transistor 141 has a drain connected to the output terminal of the differential amplifier circuit 112, and a source connected to the power supply terminal 102. The resistor 114 and the resistor 115 form a dividing circuit which divides an output voltage Vout of the output terminal 103 and outputs a divided voltage Vfb.
The related-art voltage regulator operates as follows to protect a circuit against an overcurrent. In a state in which a predetermined output voltage Vout is output from the output terminal 103, a High voltage is output from the output terminal of the differential amplifier circuit 133, and hence the NMOS transistor 132 is maintained in an ON state.
When the output terminal 103 and the ground terminal 101 are short-circuited, an output current Iout is increased. When an overcurrent state in which the output current Iout exceeds a maximum output current Im is established, a current flowing through the PMOS transistor 131 for sensing an output current is increased, and a voltage of the inverting input terminal of the differential amplifier circuit 142 is thus increased. When the voltage of the inverting input terminal of the differential amplifier circuit 142 exceeds a voltage of the reference voltage circuit 111, a voltage of the output terminal of the differential amplifier circuit 142 is gradually reduced to turn on the PMOS transistor 141 gradually. In this way, a voltage of the gate of the PMOS transistor 113 gradually becomes a voltage of the power supply terminal 102 to turn off the PMOS transistor 113.
When the output terminal 103 and the ground terminal 101 are short-circuited, the output voltage Vout is also dropped and the divided voltage Vfb is thus dropped. When the divided voltage Vfb is dropped, the output voltage of the differential amplifier circuit 133 is gradually reduced to turn off the NMOS transistor 132 gradually. Then, a current flowing through the NMOS transistor 132 is gradually reduced, whereas a current flowing through the resistor 143 is gradually increased. In other words, the drop in output voltage Vout can increase the voltage of the inverting input terminal of the differential amplifier circuit 142. Therefore, the differential amplifier circuit 142 can further turn on the PMOS transistor 141 and further turn off the PMOS transistor 113.
As described above, the related-art voltage regulator can perform overcurrent protection with use of an output voltage-output current characteristic that exhibits a fold-back characteristic.
However, the related art has a problem in that the output voltage-output current characteristic does not draw an optimal fold back line when the overcurrent protection circuit 130 starts to work.
FIG. 4 shows the output voltage-output current characteristic of the related-art voltage regulator. As apparent from FIG. 4, when the overcurrent protection circuit 130 starts to work, there is a time period during which the output voltage Vout is dropped while the maximum output current Im flows. For this reason, the PMOS transistor 113 is damaged in this period.
In order to obtain an optimal fold-back characteristic, it is required that the inverting input terminal of the differential amplifier circuit 133 have a voltage that is substantially equal to the divided voltage Vfb, and the inverting input terminal of the differential amplifier circuit 142 have a voltage that is substantially equal to the reference voltage Vref. However, the conditions are not satisfied when the overcurrent protection circuit 130 starts to work. If the divided voltage Vfb and the reference voltage Vref are substantially equal to each other when the overcurrent protection circuit 130 starts to work, although a current proportional to the reference voltage Vref needs to flow through the resistor 134, the voltage between the drain and the source of the NMOS transistor 132 in this case is substantially zero and no current flows therebetween. There is a problem in that, when the overcurrent protection circuit 130 starts to work, a potential of the source of the NMOS transistor 132, which is determined so that the drain current of the NMOS transistor 132 and a current flowing through the resistor 134 become equal to each other, does not become the divided voltage Vfb.